Analog-to-digital converters (commonly referred to as ADCs, A/Ds, or A to Ds) can refer to devices that convert a continuous physical quantity (such as voltage) to a digital number that can represent the quantity's amplitude. The result can be a sequence of digital values that have been converted from a continuous-time and continuous-amplitude analog signal to a discrete-time and discrete-amplitude digital signal. Additionally, the conversion can involve quantization of the input that can lead to the introduction of a small amount of error.
Quantization error can refer to the noise introduced by quantization in an ideal ADC. It can refer to a rounding error between the analog input voltage to the ADC and the output digitized value. These errors can be measured in a unit called the least significant bit (LSB). For example, in an eight-bit ADC, an error of one LSB is 1/256 of the full signal range, or about 0.4%.
The dynamic range of an ADC can be summarized in terms of its effective number of bits (ENOB). ENOB can refer to the number of bits of each measure the ADC returns that are, on average, not noise. An ideal ADC can have an ENOB equal to its resolution.
A successive-approximation register (SAR) ADC can refer to an ADC that uses a comparator to successively narrow a range that contains the input voltage. At each successive step, the converter can compare the input voltage to the output of an internal digital to analog converter (commonly referred to as a DAC, D/C, or D to A), which can represent the midpoint of a selected voltage range. At each step in this process, the approximation can be stored in a successive approximation register (SAR) or other type of memory.
For example, consider an input voltage of 6.3 V and an initial range of 0 to 16 V. For the first step, the input 6.3 V is compared to 8 V (the midpoint of the 0-16 V range). The comparator reports that the input voltage is less than 8 V, so the SAR and/or memory in cooperation with SAR logic circuitry can be updated to narrow the range to 0-8 V. For the second step, the input voltage is compared to 4 V (midpoint of 0-8). The comparator can then report that the input voltage is above 4 V, so the SAR and/or memory in cooperation with SAR logic circuitry can be updated to reflect the input voltage is in the range 4-8 V. For the third step, the input voltage can be compared with 6 V (halfway between 4 V and 8 V); the comparator can report the input voltage is greater than 6 volts, and the search range becomes 6-8 V. The steps can be continued until the desired resolution is reached.
Low resolution SAR ADCs (i.e. those having an ENOB less than 10 bits) can achieve high power efficiencies. However, it can be hard to maintain such high efficiency when extending the ENOB beyond 10 bits. One reason can be that high-resolution ADCs are thermal noise limited, and every 1-bit reduction in thermal noise may require approximately 4 times the analog power, leading to a poorer figures-of-merit (FOMs).
The noise in a high-resolution SAR ADC can be dominated by the comparator. Some techniques have been developed to reduce comparator noise without significantly increasing comparator power. One technique can be to arrange two comparators where a low power coarse comparator can be used on the MSB bits and a high power fine comparator can be used for the last two LSB comparisons. However, this may require that the offsets of the two comparators to be tightly matched, which can be a nontrivial situation at high resolution, even if the comparators are calibrated.
Another technique can involve a data driven noise reduction approach, where one comparator can be fired multiple times when the comparator input is small and the final decision can be made via majority voting. This technique, however, can require a carefully tuned metastability detector that can result in increased design complexity.
Yet another technique can combine redundancy with averaging. Its merit can be that it can also correct DAC settling errors. However, it may require more number of comparison cycles and additional DAC control logic. Besides, as will be shown in details in the detailed description, the SNR improvement using simple averaging may be limited in other respects.
Therefore, what are needed are devices, systems and methods that overcome challenges in the present art, some of which are described above.